Recovered Energy Logic: Device Optimization for Circuit Implementation in Silicon and Heterostructure Technologies

Recovered Energy Logic (REL) is a new family of logic that charges and discharges capacitive logic nodes in an ideally lossless fashion. To accomplish this, REL uses an AC waveform as both the system power supply and a two-phase clock. Unlike mainstream logic circuits, REL circuits require substantial current from all three terminals of a transistor. This makes BJTs and MESFETs a natural choice for implementing these circuits. Device and circuit simulations are performed for REL circuits implemented in MOSFET, MESFET and BJT technologies. The advantages and disadvantages of each technology are examined. REL circuits implemented in a 2 Jim CMOS technology function up to 20 MHz. The power-delay product of this circuit is measured at 0.3 pJ for a 3.3 Vp-p supply voltage and a 10F load capacitance. A comparable 2 gm minimum spacing bipolar process was operational up to 50 MHz, with a power-delay product of 0.8 pJ. The most promising technology implementation for REL circuitry appears to be MESFETs. Circuit simulations predict circuit performance up to 25 MHz for 2 Jim channel length devices, with a power-delay product of only 0.05 pJ. Thesis Supervisor: Martin F. Schlecht Title: Professor of Electrical Engineering and Computer Science